Switching and Routing
Calsoft Labs expertise in L2 – L3 Device areas include the following:
Routers: Core, Access , Edge Service Routers, Enterprise Routers, Gateway Routers, Residential Gateways, IP, MPLS, VPLS
Switches: Edge Switching, Small/Med Core Switching, Core Switching, Security, QoS Firewalls, VPN devices
Enterprise Voice: PBX & IP-PBX – SIP, H.323, Contact Center– ACD, IVR, NGN IVR, Unified Comms, EMS, Branch offices, Terminals – Legacy & NG IP-Phones, NAT/Firewall Traversal Solutions
Wi-Fi: 802.11a/b/g, 802.1p, Access point, Access Controllers, Mobility Mgmt
Network Management: TMN, Fault, Configuration, Accounting, Performance, Security, Element managers Network Managers
| Switching Architecture Expertise |
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| Routing Architecture Expertise |
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Cavium Processor Expertise
Calsoft Labs has leveraged the power of the Cavium processor to provide customers with solutions that provide increased performance, scalability and cost savings.
Our experience in working with the Cavium processor includes:
Application Development : Our expertise in Application development on the Cavium processor platform includes:
- High performance architecture and design expertise
- Partitioning of control, data and management plane processing on multi-cores
- Expertise in various types of software architectures such as Run-to-completion, Pipelined & Hybrid
- Expertise in various hardware elements/acceleration units such as encryption/decryption, hashing, compression/de-compression, DFA units
Tool Set : Calsoft Labs' expertise in Tool set
- Expertise in GNU development tool chain and OCTEON SDK
- Ability to develop custom make files and other build environment requirements.
- Experience with various host and target tools provided by Cavium like OCTEON Simulator
- Profiling Tools & Diagnostic Tools
- Customizing Linux and tuning
- Drivers development and optimization
- Boot-loader (u-boot) customization
- Diagnostic Software Development
- Expertise in Simple Executive Libraries and APIs
Performance Optimization and Tuning : We can help you extract the best from your processor with:
- Architectural choices
- Data Plane performance optimization techniques
- MIPS and general multi-threaded/multi-core programming techniques
- I-cache locality of reference
- L1-cache scratch pad areas
- Asynchronous (non-blocking) operations
- Using compile time options
- Buffer pool dimensioning
- OCTEON hardware accelerators to offload various software operations (for example, hash computation)


