VLSI Design & Verification Services
Calsoft labs offers state of the art VLSI design and verification services to help semiconductor vendors reduce time to market for custom ASICs and SOCs. We specialize in System architecture and partitioning, logic design, design verification and FPGA based Pre-silicon validation. Our V&V capabilities extend to bus interfaces, network interfaces, storage networking interfaces and functional blocks, up to 28 nm process.
System architecture & Partitioning
- Block / System-level modeling and Architecture
- HW-SW Co-simulation
- Microarchitecture & Design Partitioning
- Languages: C/C++, SystemC, Matlab
Front-end Design
- RTL Design & Simulation
- IP integration
- Functional verification
- Logic synthesis & Timing analysis
- Tools/Languages: Verilog-XL, NCVerilog, VCS, Modelsim, DC Ultra, PrimeTime
Design Verification
- Test bench design / development
- Test plan & Test vector development
- Block / Module / Chip-level verification
- Coverage analysis
- Tools/Languages: SystemVerilog, Vera, e, Specman, Verplex, customer proprietary DV tools
FPGA based Pre-silicon Validation
- FPGA synthesis
- Place and Route
- Timing closure
- Tools/Languages: Modelsim, Altera Quartus II & Maxplus II, Xilinx ISE, Synplify Pro, Leonardo Spectrum
Technical Competencies
